Technical Field
Embodiments described herein relate to semiconductor chips, and more particularly, to efficiently scheduling memory access requests.
Description of the Related Art
A semiconductor chip may include multiple functional blocks or units, each capable of accessing a shared memory. In some embodiments, the multiple functional units are individual dies on an integrated circuit (IC), such as a system-on-a-chip (SOC). In other embodiments, the multiple functional units are individual dies within a package, such as a multi-chip module (MCM). In yet other embodiments, the multiple functional units are individual dies or chips on a printed circuit board. A memory controller may control access to the shared memory.
The multiple functional units on the chip are sources for memory access requests sent to the memory controller. Additionally, one or more functional units may include multiple sources for memory access requests to send to the memory controller. For example, a video subsystem in a computing system may include multiple sources for video data. The design of a smartphone or computer tablet may include user interface layers, cameras, and video sources such as media players. Each of these sources may utilize video data stored in memory. A corresponding display controller may include multiple internal pixel-processing pipelines for these sources.
Each request sent from one of the multiple sources includes both overhead processing and information retrieval processing. A large number of requests from separate sources of the multiple sources on the chip may create a bottleneck in the memory subsystem. The repeated overhead processing may reduce the subsystem performance.
In some embodiments, the refresh rate of a display screen may be 60 frames-per-second, where the display screen is continually updated. However, in some cases, such as when a user is web browsing and has stopped at a single webpage for a considerable amount of time, this may cause long pauses to updates on the display screen. In addition, many areas of the chip may be inactive while the display screen is idle. However, the memory subsystem may not be able to enter a low-power mode as one or more display pipelines continue to access the shared memory. The shared memory may be off-die synchronous dynamic random access memory (SDRAM) used to store frame data in frame buffers. The accesses of the SDRAM consume an appreciable amount of power in addition to preventing the memory subsystem from entering a low-power mode.
In view of the above, methods and mechanisms for efficiently scheduling memory access requests are desired.